1. Field of the Invention
The present invention relates to a method of manufacturing and structure of a liquid crystal display device. More specifically, the present invention relates to a method for manufacturing and structure of a liquid crystal display device that prevent the occurrence of the galvanic phenomenon, which occurs when a source/drain electrode formed of metal contacts a pixel electrode formed of ITO (Indium Tin Oxide).
2. Description of the Background Art
Amorphous silicon (a-Si) TFT LCDs (Thin Film Transistor Liquid Crystal Displays) are increasingly being used in more diverse applications such as notebook PCs and desk top monitors. The growth of the TFT-LCD industry along with wider acceptance of TFT-LCD related applications have occurred because of the improvements in screen resolution and screen size of TFT LCDs. Further, the key to sustaining this growth trend is manufacturing TFT LCDs with greater productivity so that the price of TFT LCDs becomes more 1affordable to consumers. To realize significant gains in productivity, the manufacturing process must be simplified, and this can only occur if there is cooperation among all those involved in the manufacture of LCDs.
FIGS. 1A-1C are cross-sectional views illustrating a process for manufacturing a LCD according to the related art.
Referring to FIG. 1A, a buffer layer 102 is formed on an insulating substrate 100 such as glass. Thereafter, polysilicon is deposited on the buffer layer 102. The polysilicon is then patterned by etching a selected portion so that the patterned polysilicon forms an active layer 108. Alternatively, the active layer 108 may be formed by depositing amorphous silicon and then crystallizing it using laser radiation. Thereafter, a gate insulating layer 106 is formed on the buffer layer 102 and covers the active layer 108. Next, a metal film is deposited on the gate insulating layer 106 by a method such as a sputtering process. The metal film is then patterned by an etching process and defines a gate electrode 110.
The gate electrode 110 is used as an ion-blocking mask while the entire surface of the structure is heavily doped with N type or P type impurities 112. The doping process creates an active layer 108 on each side of the gate electrode 110, thus forming an impurity region 108a. The region 108a will be used later as a source/drain region.
Referring to FIG. 1B, after a first protective layer 120 is formed on the gate insulating layer 106, a first contact hole h1 is formed, which leaves the source/drain region 108a exposed. The first contact hole h1, formed within the first protective layer 120, will be used as an electrical passage that connects the source/drain region 108a to a source/drain electrode 122.
The source/drain electrode 122 is formed by depositing a metal film on the first protective layer 120 and patterning the metal film via an etching process so that the patterned metal film covers the first contact hole h1. Note that the metal film is usually made of aluminum.
Referring to FIG. 1C, a second protective layer 124 is formed so as to cover the entire surface of the structure. A second contact hole h2 is now created which exposes the source/drain electrode 122. This second contact hole h2, formed within the second protective layer 124, will be used as a passage for electrically connecting the source/drain electrode 122 and a metal connector line 126.
The metal connector line 126 is formed by depositing an ITO on the second protective layer 124 and then patterning the ITO via an etching process so that the patterned ITO covers the second contact hole h2. By this process, the metal connector line 126 is now connected to the source/drain electrode 122.
As described above, the ITO is deposited directly on the source/drain electrode 122. Further, the ITO penetrates into the material forming the source/drain electrode due to the heat generated during the deposition process. However, this penetration results in the galvanic phenomenon occurring.
Additionally, the related art process tries to control the extent of the galvanic phenomenon by minimizing the contact area between the source/drain electrode and the metal connector line. Minimizing the contact area requires that the protective layer and the contact hole be formed in two steps. However, a two-step process results in an extremely complex manufacturing process and significantly increases the time and expense required for manufacturing the liquid crystal display device.
To overcome the problems described above, preferred embodiments of the present invention provide a thin film transistor and a method of forming a thin film transistor in which a galvanic phenomenon is prevented without requiring additional etching steps.
According to one preferred embodiment of the present invention, a method for manufacturing a thin film transistor includes providing a substrate including a source/drain electrode and a connector line and forming a metal oxide layer between the source/drain electrode and the connector line.
According to another preferred embodiment of the present invention, a method for manufacturing a thin film transistor having a source/drain electrode on an insulating substrate includes forming a conductive layer to cover the source/drain electrode, heat treating the conductive layer in an oxygen atmosphere to form a metal oxide layer and forming a metal connector line on the metal oxide layer such that the metal connector line and the source/drain electrode are connected via the metal oxide layer.
According to another preferred embodiment of the present invention, a method for manufacturing a thin film transistor having a source/drain electrode on an insulating substrate includes forming a data line on an insulating substrate, the data line being provided with a source electrode, forming an interlevel insulating layer on the insulating substrate so as to cover the data line, forming an active layer on the interlevel insulating layer, depositing a gate insulating layer on the active layer to form a gate electrode, selectively doping the active layer with impurities to form a source/drain region, forming a protective layer so to cover the interlevel layer, the active layer and the gate insulating layer, etching the gate insulating layer and the protective layer so as to expose the source electrode and the source/drain region, forming a conductive layer on the interlevel layer, the active layer, the gate insulating layer, the protective layer, the source electrode and the source/drain region, heat treating the conductive layer in an oxygen atmosphere to form a metal oxide layer, and forming a metal connector line on the metal oxide layer.
Another preferred embodiment provides a thin film transistor which includes an insulating substrate, a source/drain electrode on the insulating substrate, and a conductive layer that covers at least the source/drain electrode, and which defines a metal oxide layer after being heat treated.
In the invention, the thin film transistor has an insulating substrate, a source/drain electrode over a source/drain active region on a supporting surface of the insulating substrate, and a protective layer over portions of the source/drain active region and a gate. The protective layer has via holes through which the source/drain electrode extends. A conductive layer covers the source/drain electrode and the supporting surface of the insulating substrate, and the conductive layer includes a metal oxide layer entirely covering the source drain electrode and entirely covering an upper surface of the protective layer. A metal connector line is formed on the metal oxide layer such that the metal connector line and the source/drain electrode are connected via the metal oxide layer.
Various other features, element, and advantages of the present invention will be readily appreciated as the same becomes better understood with reference to the following detailed description of preferred embodiments when considered in connection with accompanying drawings.